Low-correlation low-cost stochastic number generators for stochastic computing

Stochastic computing provides low-area and fault- tolerant computing circuits. However, the required stochastic number generators (SNGs) in these circuits are area consuming and can diminish their overall saving in hardware size, particularly if several SNGs are required. A SNG circuit consists of two parts: a random number source (RNS), e.g., a linear feedback shift register (LFSR), and a probability converter circuit (PCC), e.g., a comparator. In this paper, we propose area-efficient SNGs by sharing the permuted output of one RNS among several SNGs. With no hardware overhead, the proposed architecture generates random bit streams with minimum stochastic computing correlation (SCC). Compared to the circular shifting approach presented in recent prior work, our approach produces stochastic bit streams with 52% and 67% less average SCC when a 8-bit and a 10-bit LFSR are shared between two SNGs, respectively. We evaluated the proposed method for several applications. The results show that, compared to prior work, our approach yields lower MSE values with the same (or even lower) area-cost.