In MIMD (Multiple Instruction stream. Multiple Data stream) execution, each processor has its awn state. Although these states are generally considered to be independent entities, it is also possible to view the set of processor states at a particular time as single, aggregate, "Meta State." Once a program has been converted into a single finite automaton based on Meta States, only a single program counter is needed. Hence, it is possible to duplicate the MIMD execution using SIMD (Single Instruction stream, Multiple Data stream) hardware without the overhead of interpretation or even of having each processing element keep a copy of the MIMD code. In this paper, we present an algorithm for Meta-State Conversion (MSC) and explore some properties of the technique.
|Number of pages||10|
|Journal||Proceedings of the International Conference on Parallel Processing|
|State||Published - 1993|
|Event||1993 International Conference on Parallel Processing, ICPP 1993 - Syracuse, United States|
Duration: Aug 16 1993 → Aug 20 1993
Bibliographical noteFunding Information:
This work was supported in part by the Office of Naval Research (ONR) umder grant number N00014-91-J-4013 and by the National Science Foundation (NSF) under award number 901569-CDA.
Perhaps the most obvious way to make SIMD hardware mimic MIMD execution is to write a SIMD program that will interpretively execute a MIMD instruction set. In the simplest terms, such an interpreter has a data structure, replicated in each SIMD PE, that corresponds to the internal registers of each MIMD processor. Likewise, each PE's memory holds a copy of the MIMD code to be executed. Hence, the interpreter struc¬ ture can be as simple as: * This work was supported in part by the Office of Naval Research (ONR) under grant number N0OO14-91-J-4O13 and by the National Science Foundation (NSF) under award number 9015696-CDA.
© 1993 IEEE.
ASJC Scopus subject areas
- Mathematics (all)
- Hardware and Architecture