Multi-level metal CMOS manufacturing with deuterium for improved hot carrier reliability

This paper reports new experimental findings that are critical for the integration of deuterium post-metal anneals to manufacturing multi-level metal CMOS integrated circuits. Process optimization experiments are performed with anneal temperature (400-450 C), time (0.5-5 hr), and ambient (10-100% D₂) being varied. The first demonstration of the large hydrogen/deuterium isotope effect in multi-level metal/dielectric MOS systems is reported. An optimized deuterium anneal process for manufacturing multi-level metal/dielectric MOS systems results in 50-100 fold improvement in channel hot carrier lifetime. The proposed deuterium post-metal anneal process is suitable for manufacturing high performance CMOS (analog and digital) products and is fully compatible with traditional integrated circuit manufacturing. It is also shown that the deuterium/hydrogen isotope effect is a general property of MOS wear-out. This conclusion is reached by comparing the degradation dynamics of many transistor structures from various CMOS technologies. Physical insight into the transistor degradation mechanisms is provided via fundamental STM Si-H(D) desorption experiments and physics based simulations.