Abstract
There are many ways to reduce power consumed in performing a computation. Most focus on making each gate more power efficient. In contrast, the current work focuses on directly reducing the number of gate-level operations needed to produce each word-level result.Compiler optimization of computations at the gate level exposes many redundancies that are not apparent when optimizing word-level operations. In the proposed architecture, all operations on multi-bit data values are performed bit serially. Thus, a k-bit add takes O(k) clock cycles. However, by doing each operation SIMD-parallel on n data, n k-bit operations also complete in O(k) clock cycles using only O(n) gates per clock. Further improvement can be made by using regular expression patterns to represent the n values in each bit position; not only does this compress the data, but it also allows many gate-level operations to be performed directly on the patterns without expanding them to bit vectors.
Original language | English |
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Title of host publication | 2019 10th International Green and Sustainable Computing Conference, IGSC 2019 |
ISBN (Electronic) | 9781728154169 |
DOIs | |
State | Published - Oct 2019 |
Event | 10th International Green and Sustainable Computing Conference, IGSC 2019 - Alexandria, United States Duration: Oct 21 2019 → Oct 24 2019 |
Publication series
Name | 2019 10th International Green and Sustainable Computing Conference, IGSC 2019 |
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Conference
Conference | 10th International Green and Sustainable Computing Conference, IGSC 2019 |
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Country/Territory | United States |
City | Alexandria |
Period | 10/21/19 → 10/24/19 |
Bibliographical note
Publisher Copyright:© 2019 IEEE.
Keywords
- compiler optimization
- gate-level logic optimization
- green computer architecture
- just in time compilation
- low power
- regular expression
ASJC Scopus subject areas
- Computer Science Applications
- Hardware and Architecture
- Renewable Energy, Sustainability and the Environment