Pathway to Increase the Tolerance of Organic Transistors to Semiconductor Purity

Organic semiconductors (OSCs) have attracted rapidly growing interest given their potential to create innovative optoelectronic applications. One major drawback is the sensitivity of the electrical properties to the presence of impurities in the OSC film: even small traces can significantly alter the properties of the OSC layer by introducing electronic trapping states, leading to efficiency losses and degraded charge carrier mobility. Since impurities can be introduced at many stages of device fabrication, from synthetic impurities to process solvents to the lining on syringes used to deposit solutions, identifying device structures that are more tolerant of their presence is necessary. Here, we employ a data-driven device design, wherein simulations are combined with experiment to reveal organic field-effect transistor (OFET) geometries that enable the use of lower standards of semiconductor purity without impacting the performance. The phenomenon is attributed to how the filling of trap states is modulated by the gate potential. Guided by the simulation results, we were able to recover the performance of a pure device in OFETs with optimal geometry containing 2% known impurity. These results provide a pathway for developing high-performance organic devices at a lower cost by adopting a device architecture that is more tolerant of defects..