Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function

Yasuhiro Takahashi; Hiroki Koyasu; S. Dinesh Kumar; Himanshu Thapliyal

doi:10.1109/ISVLSI.2019.00086

Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function

Yasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.

Original language	English
Title of host publication	Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Pages	443-446
Number of pages	4
ISBN (Electronic)	9781538670996
DOIs	https://doi.org/10.1109/ISVLSI.2019.00086
State	Published - Jul 2019
Event	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 - Miami, United States Duration: Jul 15 2019 → Jul 17 2019

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2019-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Country/Territory	United States
City	Miami
Period	7/15/19 → 7/17/19

Bibliographical note

Funding Information:
This work was supported by VLSI Design and Educational Center (VDEC), the University of Tokyo in collaboration with Cadence Corporation and Synopsys, Inc. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with ROHM Corporation and Toppan Printing Corporation.

Publisher Copyright:
© 2019 IEEE.

Keywords

Adiabatic logic
PUF
hardware security
low-power

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISVLSI.2019.00086

Cite this

Takahashi, Y., Koyasu, H., Kumar, S. D., & Thapliyal, H. (2019). Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. In Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 (pp. 443-446). [8839442] (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July). https://doi.org/10.1109/ISVLSI.2019.00086

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title = "Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function",

abstract = "Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.",

keywords = "Adiabatic logic, PUF, hardware security, low-power",

author = "Yasuhiro Takahashi and Hiroki Koyasu and Kumar, {S. Dinesh} and Himanshu Thapliyal",

note = "Funding Information: This work was supported by VLSI Design and Educational Center (VDEC), the University of Tokyo in collaboration with Cadence Corporation and Synopsys, Inc. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with ROHM Corporation and Toppan Printing Corporation. Publisher Copyright: {\textcopyright} 2019 IEEE.; 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 ; Conference date: 15-07-2019 Through 17-07-2019",

year = "2019",

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doi = "10.1109/ISVLSI.2019.00086",

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Takahashi, Y, Koyasu, H, Kumar, SD & Thapliyal, H 2019, Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. in Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019., 8839442, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2019-July, pp. 443-446, 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, United States, 7/15/19. https://doi.org/10.1109/ISVLSI.2019.00086

Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. / Takahashi, Yasuhiro; Koyasu, Hiroki; Kumar, S. Dinesh et al.
Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. 2019. p. 443-446 8839442 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Koyasu, Hiroki

AU - Kumar, S. Dinesh

AU - Thapliyal, Himanshu

N1 - Funding Information: This work was supported by VLSI Design and Educational Center (VDEC), the University of Tokyo in collaboration with Cadence Corporation and Synopsys, Inc. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with ROHM Corporation and Toppan Printing Corporation. Publisher Copyright: © 2019 IEEE.

PY - 2019/7

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N2 - Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.

AB - Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.

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Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

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Cite this