TY - GEN
T1 - QUALPUF
T2 - 11th Annual Cyber and Information Security Research Conference, CISRC 2016
AU - Dinesh Kumar, S.
AU - Thapliyal, Himanshu
PY - 2016/4/5
Y1 - 2016/4/5
N2 - In the recent years, silicon based Physical Unclonable Function (PUF) has evolved as one of the popular hardware security primitives. PUFs are a class of circuits that use the inherent variations in the Integrated Circuit (IC) manufacturing process to create unique and unclonable IDs. There are various security related applications of PUFs such as IC counterfeiting, piracy detection, secure key management etc. In this paper, we are presenting a novel QUasi-Adiabatic Logic based PUF (QUALPUF) which is designed using energy recovery technique. To the best of our knowledge, this is the first work on the hardware design of PUF using adiabatic logic. The proposed design is energy efficient compared to recent designs of hardware PUFs proposed in the literature. Further, we are proposing a novel bit extraction method for our proposed PUF which improves the space set of challenge-response pairs. QUALPUF is evaluated in security metrics including reliability, uniqueness, uniformity and bit-aliasing. Power and area of QUALPUF is also presented. SPICE simulations show that QUALPUF consumes 0.39μWatt of power to generate a response bit.
AB - In the recent years, silicon based Physical Unclonable Function (PUF) has evolved as one of the popular hardware security primitives. PUFs are a class of circuits that use the inherent variations in the Integrated Circuit (IC) manufacturing process to create unique and unclonable IDs. There are various security related applications of PUFs such as IC counterfeiting, piracy detection, secure key management etc. In this paper, we are presenting a novel QUasi-Adiabatic Logic based PUF (QUALPUF) which is designed using energy recovery technique. To the best of our knowledge, this is the first work on the hardware design of PUF using adiabatic logic. The proposed design is energy efficient compared to recent designs of hardware PUFs proposed in the literature. Further, we are proposing a novel bit extraction method for our proposed PUF which improves the space set of challenge-response pairs. QUALPUF is evaluated in security metrics including reliability, uniqueness, uniformity and bit-aliasing. Power and area of QUALPUF is also presented. SPICE simulations show that QUALPUF consumes 0.39μWatt of power to generate a response bit.
KW - Adiabatic logic
KW - Hardware assurance
KW - Hardware security
KW - PUF
KW - Ultra-low-power
UR - http://www.scopus.com/inward/record.url?scp=84968616778&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84968616778&partnerID=8YFLogxK
U2 - 10.1145/2897795.2897798
DO - 10.1145/2897795.2897798
M3 - Conference contribution
AN - SCOPUS:84968616778
T3 - Proceedings of the 11th Annual Cyber and Information Security Research Conference, CISRC 2016
BT - Proceedings of the 11th Annual Cyber and Information Security Research Conference, CISRC 2016
Y2 - 5 April 2016 through 7 April 2016
ER -