Reduction of cache coherence overhead by compiler data layout and loop transformation

Y. J. Ju, H. Dietz

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

25 Scopus citations

Abstract

This paper presents a systematic approach that integrates compiler optimization of data layout and traditional loop transformations to reduce cache coherence overhead. A formal model based on an interference graph, overview of the optimization algorithms, and an example are given. Excerpts from an empirical evaluation of the complexity of the compiler analysis, and the simulation study of the resulting reductions in bus traffic and execution time, are also presented. Additional details appear in [7].

Original languageEnglish
Title of host publicationLanguages and Compilers for Parallel Computing - 4th International Workshop, Proceedings
EditorsUtpal Banerjee, David Gelernter, Alex Nicolau, David Padua
Pages344-358
Number of pages15
DOIs
StatePublished - 1992
Event4th Workshop on Languages and Compilers for Parallel Computing, 1991 - Santa Clara, United States
Duration: Aug 7 1991Aug 9 1991

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume589 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference4th Workshop on Languages and Compilers for Parallel Computing, 1991
Country/TerritoryUnited States
CitySanta Clara
Period8/7/918/9/91

Bibliographical note

Publisher Copyright:
© 1992, Springer Verlag. All rights reserved.

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science

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