Abstract
This paper presents a systematic approach that integrates compiler optimization of data layout and traditional loop transformations to reduce cache coherence overhead. A formal model based on an interference graph, overview of the optimization algorithms, and an example are given. Excerpts from an empirical evaluation of the complexity of the compiler analysis, and the simulation study of the resulting reductions in bus traffic and execution time, are also presented. Additional details appear in [7].
| Original language | English |
|---|---|
| Title of host publication | Languages and Compilers for Parallel Computing - 4th International Workshop, Proceedings |
| Editors | Utpal Banerjee, David Gelernter, Alex Nicolau, David Padua |
| Pages | 344-358 |
| Number of pages | 15 |
| DOIs | |
| State | Published - 1992 |
| Event | 4th Workshop on Languages and Compilers for Parallel Computing, 1991 - Santa Clara, United States Duration: Aug 7 1991 → Aug 9 1991 |
Publication series
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volume | 589 LNCS |
| ISSN (Print) | 0302-9743 |
| ISSN (Electronic) | 1611-3349 |
Conference
| Conference | 4th Workshop on Languages and Compilers for Parallel Computing, 1991 |
|---|---|
| Country/Territory | United States |
| City | Santa Clara |
| Period | 8/7/91 → 8/9/91 |
Bibliographical note
Publisher Copyright:© 1992, Springer Verlag. All rights reserved.
ASJC Scopus subject areas
- Theoretical Computer Science
- Computer Science (all)