@inproceedings{8e006522342a45ff9286b841a63dc73f,

title = "Reversible logic synthesis of half, full and parallel subtractors",

abstract = "In a reversible gate, the number of inputs is equal to the number of outputs and there is a one-to-one mappings between input vectors and output vectors. Thus in reversible gate input vector states can be always uniquely reconstructed from the output vector states. This paper proposes a reversible half subtractor using reversible Fredkin and Feynman gate. The reversible half subtractor is used to design reversible full subtractor. The reversible half and full subtractor are further used to build reversible binary parallel subtractor. This is the first attempt to design reversible subtractors as far our knowledge and known literature is concerned. Earlier attempts were related to design of adders only.",

keywords = "Parallel binary reversible subtractor, Quantum circuits, Reversible logic, Reversible subtractor",

author = "Himanshu Thapliyal and Srinivas, {M. B.} and Arabnia, {Hamid R.}",

year = "2005",

language = "English",

isbn = "9781932415537",

series = "Proceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05",

pages = "165--171",

booktitle = "Proceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05",

note = "2005 International Conference on Embedded Systems and Applications, ESA'05 ; Conference date: 27-06-2005 Through 30-06-2005",

}