Abstract
Deep Neural Networks (DNNs) predominantly rely on General Matrix Multiply (GEMM) kernels, which are often accelerated using specialized hardware architectures. Recently, analog photonic GEMM accelerators have emerged as a promising alternative, offering vastly superior speed and energy efficiency compared to traditional electronic accelerators. However, these photonic cannot support wider than 4-bit integer operands due to their inherent tradeoffs between analog dynamic range and parallelism. This is often inadequate for DNN training as at least 8-bit wide operands are deemed necessary to prevent significant accuracy drops. To address these limitations, we introduce a scalable photonic GEMM accelerator named SPOGA. SPOGA utilizes enhanced features such as analog summation of homo-dyne optical signals and in-transduction positional weighting of operands. By employing an extended optical-analog dataflow that minimizes overheads associated with bit-sliced integer arithmetic, SPOGA supports byte-size integer GEMM kernels, achieving significant improvements in throughput, latency, and energy efficiency. Specifically, SPOGA demonstrates up to 14.4x, 2 x, and 28.5 x improvements in frames-per-second (FPS), FPS/Watt, and FPS/Watt/mm2 respectively, compared to existing state-of-the-art photonic solutions.
Original language | English |
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Title of host publication | 2024 IEEE Computer Society Annual Symposium on VLSI |
Subtitle of host publication | Emerging VLSI Technologies and Architectures, ISVLSI 2024 |
Editors | Himanshu Thapliyal, Jurgen Becker |
Pages | 409-414 |
Number of pages | 6 |
ISBN (Electronic) | 9798350354119 |
DOIs | |
State | Published - 2024 |
Event | 2024 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2024 - Knoxville, United States Duration: Jul 1 2024 → Jul 3 2024 |
Publication series
Name | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI |
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ISSN (Print) | 2159-3469 |
ISSN (Electronic) | 2159-3477 |
Conference
Conference | 2024 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2024 |
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Country/Territory | United States |
City | Knoxville |
Period | 7/1/24 → 7/3/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- Accelerator
- Bit Slicing
- Deep Learning
- General Matrix Multiplication
- Silicon Photonics
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering
- Electrical and Electronic Engineering