Abstract
Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wavelength-division multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This chapter presents a novel framework called SOTERIA that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. With a minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP) our approach can significantly enhance the hardware security in DWDM-based PNoCs.
| Original language | English |
|---|---|
| Title of host publication | Network-on-Chip Security and Privacy |
| Pages | 399-421 |
| Number of pages | 23 |
| ISBN (Electronic) | 9783030691318 |
| DOIs | |
| State | Published - May 3 2021 |
Bibliographical note
Publisher Copyright:© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021. All rights reserved.
Keywords
- Chip multiprocessor
- Denial of Service
- Electrical NoC
- Energy-delay product
- Error correction code
- Gateway interface
- Hardware Trojan
- Hardware security
- Link-level security
- Malicious detector
- Malicious modulator
- Microring resonator
- Network-on-Chip
- NoC
- Photonic NoC
- Photonic waveguide
- Process variation
- Snooping attack
- Unicast communication
- Wireless NoC
ASJC Scopus subject areas
- General Engineering
- General Computer Science