SOTERIA: Exploiting process variations to enhance hardware security with photonic NoC architectures

Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Varun Bhat; Sudeep Pasricha

doi:10.1145/3195970.3196118

SOTERIA: Exploiting process variations to enhance hardware security with photonic NoC architectures

Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

19 Scopus citations

Abstract

Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a novel framework called SOTERIA. that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDMbased PNoCs with minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP).

Original language	English
Title of host publication	Proceedings of the 55th Annual Design Automation Conference, DAC 2018
DOIs	https://doi.org/10.1145/3195970.3196118
State	Published - Jun 24 2018
Event	55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States Duration: Jun 24 2018 → Jun 29 2018

Publication series

Name	Proceedings - Design Automation Conference
Volume	Part F137710
ISSN (Print)	0738-100X

Conference

Conference	55th Annual Design Automation Conference, DAC 2018
Country/Territory	United States
City	San Francisco
Period	6/24/18 → 6/29/18

Bibliographical note

Publisher Copyright:
© 2018 Association for Computing Machinery.

Keywords

Hardware Security
Photonic NoCs
Process Variations

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

Access to Document

10.1145/3195970.3196118

Cite this

@inproceedings{f9413396c6284a659248618e704d30b2,

title = "SOTERIA: Exploiting process variations to enhance hardware security with photonic NoC architectures",

abstract = "Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a novel framework called SOTERIA. that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDMbased PNoCs with minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP).",

keywords = "Hardware Security, Photonic NoCs, Process Variations",

author = "Chittamuru, {Sai Vineel Reddy} and Thakkar, {Ishan G.} and Varun Bhat and Sudeep Pasricha",

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year = "2018",

month = jun,

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doi = "10.1145/3195970.3196118",

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Chittamuru, SVR, Thakkar, IG, Bhat, V & Pasricha, S 2018, SOTERIA: Exploiting process variations to enhance hardware security with photonic NoC architectures. in Proceedings of the 55th Annual Design Automation Conference, DAC 2018., a81, Proceedings - Design Automation Conference, vol. Part F137710, 55th Annual Design Automation Conference, DAC 2018, San Francisco, United States, 6/24/18. https://doi.org/10.1145/3195970.3196118

SOTERIA: Exploiting process variations to enhance hardware security with photonic NoC architectures. / Chittamuru, Sai Vineel Reddy; Thakkar, Ishan G.; Bhat, Varun et al.
Proceedings of the 55th Annual Design Automation Conference, DAC 2018. 2018. a81 (Proceedings - Design Automation Conference; Vol. Part F137710).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Thakkar, Ishan G.

AU - Bhat, Varun

AU - Pasricha, Sudeep

PY - 2018/6/24

Y1 - 2018/6/24

N2 - Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a novel framework called SOTERIA. that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDMbased PNoCs with minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP).

AB - Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a novel framework called SOTERIA. that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDMbased PNoCs with minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP).

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KW - Photonic NoCs

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SOTERIA: Exploiting process variations to enhance hardware security with photonic NoC architectures

Abstract

Publication series

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Bibliographical note

Keywords

ASJC Scopus subject areas

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