Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ

Hybridization of Magnetic Tunnel Junction (MTJ) devices and CMOS transistors are being investigated to design Logic-In-Memory (LIM) architecture. However, hybrid CMOS/MTJ based LIM architecture suffers from significant power consumption due to charging and discharging of a capacitive output load. Adiabatic logic is one of the low-power design techniques to design energy-efficient hardware. Therefore, we apply the adiabatic logic in hybrid CMOS/MTJ based designs to propose the novel concept of Adiabatic Logic-In-Memory (ALIM) circuits. The proposed ALIM based CMOS/MTJ circuits have reduced dynamic power consumption as compared to the existing CMOS/MTJ circuits by using the energy recovery property. As a case study, we have designed an ALIM based magnetic full adder. Simulations are performed using 45nm CMOS technology with perpendicular anisotropy CoFeB/MgOMTJ model using Cadence Spectre simulator. From the simulation results, it is verified that the proposed ALIM based Magnetic Full Adder (MFA) saves 37% of energy and 43% of power as compared to the existing Pre-Charge Sense Amplifier (PCSA) based MFA. Further, the proposed ALIM based MFA also saves 38 % of the area as compared to the existing PCSA based MFA due to reduction in the number of transistors. The low-area, low-power and low-energy consumption makes the proposed ALIM architecture an the attractive choice to design low-power circuits.