Abstract
The design of a debugging and performance analysis system that includes a specification language for process-level events and hardware for nonintrusive identification of these events during the execution of parallel and distributed applications for a nonshared memory system is presented. The design is based on a formal event/action model and a layered architecture model that have been previously presented. Background, related work, and specification, and identification of events are discussed.
| Original language | English |
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| Pages | 476-483 |
| Number of pages | 8 |
| State | Published - 1990 |
| Event | Proceedings of the 10th International Conference on Distributed Computing Systems - ICDCS-10 - Paris, Fr Duration: May 28 1990 → Jun 1 1990 |
Conference
| Conference | Proceedings of the 10th International Conference on Distributed Computing Systems - ICDCS-10 |
|---|---|
| City | Paris, Fr |
| Period | 5/28/90 → 6/1/90 |
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Networks and Communications