Abstract
Data movement remains the biggest energy and performance bottleneck for accelerating machine learning workloads in modern computing platforms. We introduce STAR, a mixed analog/stochastic-based in-DRAM accelerator for convolutional neural network (CNN) inference tasks. We propose lightweight modifications and circuits into conventional DRAM arrays, to support stochastic computing for multiplications and devise a novel in-DRAM metal-on-metal capacitor for analog accumulations. STAR combines in-sense-amplifier and near-subarray computing to overcome challenges inherent in prior in-DRAM and stochastic-based accelerators. Experimental results indicate that STAR exhibits at least 2.1× lower latency, 2.6× better computational efficiency, and 30% higher power efficiency compared to state-of-the-art in-DRAM accelerators.
Original language | English |
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Pages (from-to) | 1 |
Number of pages | 1 |
Journal | IEEE Design and Test |
DOIs | |
State | Accepted/In press - 2024 |
Bibliographical note
Publisher Copyright:IEEE
Keywords
- Arithmetic
- Capacitors
- Circuits
- Computer architecture
- convolution neural networks
- in-DRAM processing
- Logic gates
- Random access memory
- Stars
- stochastic computing
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering