Static barrier MIMD: Architecture and performance analysis

In this paper, we describe and analyze the performance of a new architectural construct - an efficient synchronization mechanism called “Static Barrier MIMD” or SBM. Unlike traditional barrier synchronization, the proposed barriers are designed to allow static (compile-time) code scheduling to eliminate some synchronizations. The static barrier MIMD hardware is more general than most hardware barrier mechanisms, allowing any subset of the processors to participate in each barrier. The barriers execute in a small number of clock ticks, and processors proceed simultaneously past the barrier. The performance of idealized barrier schedules is examined to gain insights into code scheduling for barrier MIMD machines.