Static synchronization beyond VLIW

The authors propose a new kind of architecture, the static barrier MIMD (SBM), which can be viewed as further generalization of the parallel execution abilities of static synchronization machines. Barrier MIMDs are asynchronous multiple-instruction-stream multiple-data-stream architectures capable of parallel execution of loops, subprogram calls, and variable-execution-time instructions. However, instead of using barriers as a synchronization mechanism, the proposed barrier hardware is used to impose static timing constraints. Since the compiler can know at compile time all instructions which each processor could be executing when a particular conceptual synchronization operation is needed, it can resolve most synchronizations by using VLIW (very-long-instruction word)-like compile-time instruction scheduling, without the use of a runtime synchronization mechanism. The effect is that the proposed barrier mechanism greatly extends the generality of efficient static scheduling without adding a significant hardware cost. Both the barrier architecture and the supporting compiler technology are discussed.