Abstract
A stochastic number generator (SNG) is used to convert binary radix encoded numbers to bit-streams in stochastic computing. An SNG consists of two components: a random number source (RNS) and a probability conversion circuit (PCC). While both the hardware area overhead and hardware cost for arithmetic operations are significantly less in stochastic computing than in binary computing, the area overhead and cost for an SNG is substantial. In this paper, we propose two minimum PCC (MPCC) designs, with minimum logic in terms of 2-input gates, that reduce the hardware cost of an SNG. The proposed MPCCs generate bit-streams with very low correlation when used with two SNGs that share one RNS. Compared to prior work, the proposed MPCCs can reduce the hardware cost for a 12-bit SNG up to 67%.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 |
| Pages | 49-54 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781665439466 |
| DOIs | |
| State | Published - Jul 2021 |
| Event | 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 - Tampa, United States Duration: Jul 7 2021 → Jul 9 2021 |
Publication series
| Name | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI |
|---|---|
| Volume | 2021-July |
| ISSN (Print) | 2159-3469 |
| ISSN (Electronic) | 2159-3477 |
Conference
| Conference | 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 |
|---|---|
| Country/Territory | United States |
| City | Tampa |
| Period | 7/7/21 → 7/9/21 |
Bibliographical note
Publisher Copyright:© 2021 IEEE.
Keywords
- Stochastic computing
- area-efficiency
- cost reduction
- linear feedback shift register sharing
- stochastic number generator
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering
- Electrical and Electronic Engineering