Stochastic Number Generators with Minimum Probability Conversion Circuits

Chris Collinsworth, Sayed Ahmad Salehi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A stochastic number generator (SNG) is used to convert binary radix encoded numbers to bit-streams in stochastic computing. An SNG consists of two components: a random number source (RNS) and a probability conversion circuit (PCC). While both the hardware area overhead and hardware cost for arithmetic operations are significantly less in stochastic computing than in binary computing, the area overhead and cost for an SNG is substantial. In this paper, we propose two minimum PCC (MPCC) designs, with minimum logic in terms of 2-input gates, that reduce the hardware cost of an SNG. The proposed MPCCs generate bit-streams with very low correlation when used with two SNGs that share one RNS. Compared to prior work, the proposed MPCCs can reduce the hardware cost for a 12-bit SNG up to 67%.

Original languageEnglish
Title of host publicationProceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Pages49-54
Number of pages6
ISBN (Electronic)9781665439466
DOIs
StatePublished - Jul 2021
Event20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021 - Tampa, United States
Duration: Jul 7 2021Jul 9 2021

Publication series

NameProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume2021-July
ISSN (Print)2159-3469
ISSN (Electronic)2159-3477

Conference

Conference20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Country/TerritoryUnited States
CityTampa
Period7/7/217/9/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

  • Stochastic computing
  • area-efficiency
  • cost reduction
  • linear feedback shift register sharing
  • stochastic number generator

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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