Testudo: A Low Latency and High-Efficient Memory-Centric Network Using Optical Interconnect

With the continuing-scaling of future multicore processors, the performance requirements on memory access has been put forward much higher. Memory-centric network is deemed as a promising communication paradigm for core-to-memory interconnect in future multicore processors. However, the traditional electrical interconnect has the drawbacks of limited capacity, high communication delay, poor scalability and low energy efficiency, which further limits the performance improvement of the system. To support high-performance communication for memory access, we propose the Testudo architecture, an optically connected memory-centric network (MCN), which utilizes the emerging optical interconnect technology and 3D-stacking memory technology to achieve high bandwidth, low power consumption and high scalability. Testudo is designed based on multiple optical crossbar organized in a torus-like topology. Each optical crossbar is in multiple-write-multiple-read construction, which provides high connectivity for IP cores. By employing an all optical, token-based arbitration scheme with low complexity, the memory access communication is contention-free. Simulation results show that Testudo improves the performance significantly compared to the electrical mesh topology.