The new BCD subtractor and its reversible logic implementation

Himanshu Thapliyal, M. B. Srinivas

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Thus in this paper we propose a novel BCD subtracter called carry skip BCD subtracter. We also propose the reversible logic implementation of the proposed carry skip BCD subtracter. Reversible logic is emerging as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. It is being tried to design the BCD subtracter optimal in terms of number of reversible gates and garbage outputs.

Original languageEnglish
Title of host publicationAdvances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
Pages466-472
Number of pages7
DOIs
StatePublished - 2006
Event11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006 - Shanghai, China
Duration: Sep 6 2006Sep 8 2006

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4186 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006
Country/TerritoryChina
CityShanghai
Period9/6/069/8/06

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science

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