The new BCD subtractor and its reversible logic implementation

Himanshu Thapliyal; M. B. Srinivas

doi:10.1007/11859802_45

The new BCD subtractor and its reversible logic implementation

Himanshu Thapliyal, M. B. Srinivas

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Thus in this paper we propose a novel BCD subtracter called carry skip BCD subtracter. We also propose the reversible logic implementation of the proposed carry skip BCD subtracter. Reversible logic is emerging as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. It is being tried to design the BCD subtracter optimal in terms of number of reversible gates and garbage outputs.

Original language	English
Title of host publication	Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
Pages	466-472
Number of pages	7
DOIs	https://doi.org/10.1007/11859802_45
State	Published - 2006
Event	11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006 - Shanghai, China Duration: Sep 6 2006 → Sep 8 2006

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	4186 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006
Country/Territory	China
City	Shanghai
Period	9/6/06 → 9/8/06

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

Access to Document

10.1007/11859802_45

Cite this

Thapliyal, H., & Srinivas, M. B. (2006). The new BCD subtractor and its reversible logic implementation. In Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings (pp. 466-472). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4186 LNCS). https://doi.org/10.1007/11859802_45

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Thapliyal, H & Srinivas, MB 2006, The new BCD subtractor and its reversible logic implementation. in Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4186 LNCS, pp. 466-472, 11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006, Shanghai, China, 9/6/06. https://doi.org/10.1007/11859802_45

The new BCD subtractor and its reversible logic implementation. / Thapliyal, Himanshu; Srinivas, M. B.
Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. 2006. p. 466-472 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4186 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Thapliyal H, Srinivas MB. The new BCD subtractor and its reversible logic implementation. In Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. 2006. p. 466-472. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/11859802_45

The new BCD subtractor and its reversible logic implementation

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