TY - GEN
T1 - Transistor realization of reversible TSG gate and reversible adder architectures
AU - Thapliyal, Himanshu
AU - Vinod, A. P.
PY - 2006
Y1 - 2006
N2 - Reversible logic is emerging as a promising technology with applications in design of low power arithmetic and data path units for digital signal processing (DSP), quantum computing, nanotechnology, and optical computing. In this paper, the transistor realization of a new 4*4 reversible gate called "TSG" gate is presented. The proposed TSG gate has the ability to operate as a reversible full adder i.e. reversible full adder is implemented using a single gate. The transistor realizations of 1-bit reversible full adder, reversible ripple carry adder and reversible carry skip adder are also presented. In order to have the reduced transistor overhead of reversible carry skip adder, its modified design has been proposed. We also demonstrate a method to minimize the overhead in transistor implementation of reversible arithmetic units. The transistor implementation of reversible arithmetic circuits presented in this paper finds extensive applications in computationally intensive DSP tasks.
AB - Reversible logic is emerging as a promising technology with applications in design of low power arithmetic and data path units for digital signal processing (DSP), quantum computing, nanotechnology, and optical computing. In this paper, the transistor realization of a new 4*4 reversible gate called "TSG" gate is presented. The proposed TSG gate has the ability to operate as a reversible full adder i.e. reversible full adder is implemented using a single gate. The transistor realizations of 1-bit reversible full adder, reversible ripple carry adder and reversible carry skip adder are also presented. In order to have the reduced transistor overhead of reversible carry skip adder, its modified design has been proposed. We also demonstrate a method to minimize the overhead in transistor implementation of reversible arithmetic units. The transistor implementation of reversible arithmetic circuits presented in this paper finds extensive applications in computationally intensive DSP tasks.
KW - Reversible adders
KW - Reversible logic
UR - http://www.scopus.com/inward/record.url?scp=50249123992&partnerID=8YFLogxK
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U2 - 10.1109/APCCAS.2006.342478
DO - 10.1109/APCCAS.2006.342478
M3 - Conference contribution
AN - SCOPUS:50249123992
SN - 1424403871
SN - 9781424403875
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 418
EP - 421
BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 4 December 2006 through 6 December 2006
ER -