Transistor sizing for Bias-Stress instability compensation in Inkjet-Printed organic complementary inverters

We present a design approach to maintain a stable voltage transfer characteristic in inkjet-printed complementary organic thin-film transistor logic inverters via device sizing. We use transistor-level design to help achieve stable logic gates, so that performance is less dependent on processing conditions and materials properties that are difficult to control for inkjet-printed electronics. Despite bias-stress instability in the individual p-And n-Type transistors, a stable inverter switching threshold is achieved by equalizing the magnitudes of positive and negative threshold voltage shifts. Following a typical sizing approach for complementary logic, a p-To n-Transistor transconductance ratio of 0.25 places the inverter switching threshold near the center of the voltage supply range. However, we show through calculations and measured results that a ratio closer to 2.5 prevents rapid shift of the switching threshold, which is equally important for reliable inverter operation. Furthermore, we provide a design approach to size digital logic gates with arbitrary probability of output states.