Unified Management of Registers and Cache Using Liveness and Cache Bypass

C. H. Chi, H. Dietz

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


In current computer memory system hierarchy, registers and cache are both used to bridge the reference delay gap between the fast processor1989 and the slow main memory. While registers are managed by the compiler using program flow analysis, cache is mainly controlled by hardware without any program understanding. Due to the lack of coordination in managing these two memory structures, significant loss of system performance results because: In this paper, we propose an unified management of registers and cache using liveness and cache bypass. By using a single model to manage these two memory structures, most redundant copies of values in cache can be eliminated. Consequently, bus traffic and memory traffic in data cache are greatly reduced and cache effectiveness is improved.

Original languageEnglish
Pages (from-to)344-353
Number of pages10
JournalACM SIGPLAN Notices
Issue number7
StatePublished - Jun 21 1989

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design


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