Verilog Coding Style for Efficient Synthesis in FPGA

In this paper, we discuss efficient coding and design styles using Verilog from synthesis point of view. These techniques can be greatly helpful for any digital designer writing designs having speed and area considerations in his mind. Different important techniques have been addressed to enable the designer to write synthesizable codes. Apart from the synthesis, techniques are also discussed to improve the speed and area of netlist generated from the RTL codes. The prominent problem faced by the designer related to synthesis of Division and Modulus operator in FPGA has been discussed and an efficient solution has been provided.