VLIW across multiple superscalar processors on a single chip

Soohong P. Kim, Raymond R. Hoare, Henry G. Dietz

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


Advances in IC technology increase the integration density for higher clock rates and provide more opportunities for microprocessor design. In this paper, we propose a new paradigm to exploit instruction-level parallelism (ILP) across multiple superscalar processors on a single chip by taking advantages of both VLIW-style static scheduling techniques and dynamic scheduling of superscalar architecture. In the proposed paradigm, ILP is exploited by a compiler from a sequential program and this VLIW-like-parallelized code is further parallelized by 2-way superscalar engines at run-time. Superscalar processors are connected by an aggregate function network, which can enforce the necessary static timing constraints and provide appropriate inter-processor data communication mechanisms that are needed for ILP. The aggregate function operations are statically scheduled and implement not only fine-grain communication and control, but also simple global computations resembling systolic array operations within the network.

Original languageEnglish
Pages (from-to)166-175
Number of pages10
JournalParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
StatePublished - 1997
EventProceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques - San Francisco, CA, USA
Duration: Nov 10 1997Nov 14 1997

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture


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