@inproceedings{bef846d80e3048aebaa7b7aa6d9866b3,

title = "VLSI implementation of 0(n*n) sorting algorithms and their hardware comparison",

abstract = "This paper proposes the hardware implementation of 0(n*n) sorting algorithms; Bubble Sort, Insertion Sort and Selection Sort. The coding of the sorting algorithms is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that hardware implementation of Insertion sort algorithm is more efficient than Bubble Sort and Selection Sort in terms of area and speed. In hardware implementation Selection Sort has the worst propagation delay and area.",

author = "Saurabh Kotiyal and Himanshu Thapliyal and Srinivas, {M. B.} and Arabnia, {Hamid R.}",

year = "2005",

language = "English",

isbn = "9781932415629",

series = "Proceedings of the 2005 International Conference on Scientific Computing, CSC'05",

pages = "74--77",

booktitle = "Proceedings of the 2005 International Conference on Scientific Computing, CSC'05",

note = "null ; Conference date: 20-06-2005 Through 23-06-2005",

}