TY - GEN

T1 - VLSI implementation of 0(n*n) sorting algorithms and their hardware comparison

AU - Kotiyal, Saurabh

AU - Thapliyal, Himanshu

AU - Srinivas, M. B.

AU - Arabnia, Hamid R.

PY - 2005

Y1 - 2005

N2 - This paper proposes the hardware implementation of 0(n*n) sorting algorithms; Bubble Sort, Insertion Sort and Selection Sort. The coding of the sorting algorithms is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that hardware implementation of Insertion sort algorithm is more efficient than Bubble Sort and Selection Sort in terms of area and speed. In hardware implementation Selection Sort has the worst propagation delay and area.

AB - This paper proposes the hardware implementation of 0(n*n) sorting algorithms; Bubble Sort, Insertion Sort and Selection Sort. The coding of the sorting algorithms is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that hardware implementation of Insertion sort algorithm is more efficient than Bubble Sort and Selection Sort in terms of area and speed. In hardware implementation Selection Sort has the worst propagation delay and area.

UR - http://www.scopus.com/inward/record.url?scp=60749112382&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=60749112382&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:60749112382

SN - 9781932415629

T3 - Proceedings of the 2005 International Conference on Scientific Computing, CSC'05

SP - 74

EP - 77

BT - Proceedings of the 2005 International Conference on Scientific Computing, CSC'05

T2 - 2005 International Conference on Scientific Computing, CSC'05

Y2 - 20 June 2005 through 23 June 2005

ER -