VLSI implementation of RSA encryption system using Ancient Indian Vedic Mathematics

Himanshu Thapliyal, M. B. Srinivas

Research output: Contribution to journalConference articlepeer-review

9 Scopus citations


This paper proposes the hardware implementation of RSA encryption/ decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division architecture based on Straight Division algorithm of Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency. The coding is done in Verilog HDL and the FPGA synthesis is done using Xilinx Spartan library. The results show that RSA circuitry implemented using Vedic division and multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplication and division architectures.

Original languageEnglish
Article number98
Pages (from-to)888-892
Number of pages5
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume5837 PART II
StatePublished - 2005
EventVLSI Circuits and Systems II - Seville, Spain
Duration: May 9 2005May 11 2005


  • Overlay Multiplier
  • RSA encryption/decryption
  • Vedic Division
  • Vedic Mathematics

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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