Wire crossing constrained QCA circuit design using bilayer logic decomposition

A. Roohi, H. Thapliyal, R. F. DeMara

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Quantum-dot cellular automata (QCA) seek potential benefits over CMOS devices such as low-power consumption, small dimensions, and high-speed operation. Two prominent QCA concerns of wire crossing complexity and circuit robustness are addressed by developing a three-step bilayer logic decomposition (BLD) methodology to design QCA-based logic circuits. The partitioning of QCA computing operations into logic layers realises considerable improvements in complexity, area, and modularity metrics. Moreover, since larger circuits are divided into two increasingly disjoint sub-planes, verification of the functionality of the design becomes compartmentalised. Design capability of the proposed approach is illustrated and analysed by implementing an area-efficient full comparator (FC) based on a novel logic realisation. The resulting 1-bit FC achieves 32% improvement in complexity metrics in comparison with the previous optimal QCA-based FC. The related waveforms used in verification of the BLD-generated FC which are obtained by the QCADesigner simulation tool are discussed as a motivating example of the BLD methodology.

Original languageEnglish
Pages (from-to)1677-1679
Number of pages3
JournalElectronics Letters
Volume51
Issue number21
DOIs
StatePublished - Oct 8 2015

Bibliographical note

Publisher Copyright:
© 2015 The Institution of Engineering and Technology.

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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