Work-in-Progress: Efficient Low-latency Near-Memory Addition

Alexander Reaugh; Sayed Ahmad Salehi

doi:10.1109/CASES55004.2022.00023

Work-in-Progress: Efficient Low-latency Near-Memory Addition

Alexander Reaugh, Sayed Ahmad Salehi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Near-memory computing provides energy and time saving for performing bitwise-parallel operations in computing systems. Bitwise parallelism of addition, however, is restricted due to carry propagation. In this work, we propose new circuits for performing digit-wise near-memory addition for ternary data. The proposed architecture can perform carry-free addition and, despite the number of digits of the input operands, its latency is 21 memory cycles which is the lowest latency compared to prior work.

Original language	English
Title of host publication	Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022
Pages	33-34
Number of pages	2
ISBN (Electronic)	9781665472968
DOIs	https://doi.org/10.1109/CASES55004.2022.00023
State	Published - 2022
Event	2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022 - Shanghai, China Duration: Oct 7 2022 → Oct 14 2022

Publication series

Name	Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022

Conference

Conference	2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022
Country/Territory	China
City	Shanghai
Period	10/7/22 → 10/14/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

Carry-free Addition
Latency
Near-Memory Computing
Ternary Computing

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/CASES55004.2022.00023

Cite this

Reaugh, A., & Salehi, S. A. (2022). Work-in-Progress: Efficient Low-latency Near-Memory Addition. In Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022 (pp. 33-34). (Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022). https://doi.org/10.1109/CASES55004.2022.00023

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abstract = "Near-memory computing provides energy and time saving for performing bitwise-parallel operations in computing systems. Bitwise parallelism of addition, however, is restricted due to carry propagation. In this work, we propose new circuits for performing digit-wise near-memory addition for ternary data. The proposed architecture can perform carry-free addition and, despite the number of digits of the input operands, its latency is 21 memory cycles which is the lowest latency compared to prior work.",

keywords = "Carry-free Addition, Latency, Near-Memory Computing, Ternary Computing",

author = "Alexander Reaugh and Salehi, {Sayed Ahmad}",

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year = "2022",

doi = "10.1109/CASES55004.2022.00023",

language = "English",

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Reaugh, A & Salehi, SA 2022, Work-in-Progress: Efficient Low-latency Near-Memory Addition. in Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022. Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022, pp. 33-34, 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022, Shanghai, China, 10/7/22. https://doi.org/10.1109/CASES55004.2022.00023

Work-in-Progress : Efficient Low-latency Near-Memory Addition. / Reaugh, Alexander; Salehi, Sayed Ahmad.

Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022. 2022. p. 33-34 (Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Reaugh, Alexander

AU - Salehi, Sayed Ahmad

PY - 2022

Y1 - 2022

N2 - Near-memory computing provides energy and time saving for performing bitwise-parallel operations in computing systems. Bitwise parallelism of addition, however, is restricted due to carry propagation. In this work, we propose new circuits for performing digit-wise near-memory addition for ternary data. The proposed architecture can perform carry-free addition and, despite the number of digits of the input operands, its latency is 21 memory cycles which is the lowest latency compared to prior work.

AB - Near-memory computing provides energy and time saving for performing bitwise-parallel operations in computing systems. Bitwise parallelism of addition, however, is restricted due to carry propagation. In this work, we propose new circuits for performing digit-wise near-memory addition for ternary data. The proposed architecture can perform carry-free addition and, despite the number of digits of the input operands, its latency is 21 memory cycles which is the lowest latency compared to prior work.

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KW - Latency

KW - Near-Memory Computing

KW - Ternary Computing

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M3 - Conference contribution

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T3 - Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022

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BT - Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022

Y2 - 7 October 2022 through 14 October 2022

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Reaugh A, Salehi SA. Work-in-Progress: Efficient Low-latency Near-Memory Addition. In Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022. 2022. p. 33-34. (Proceedings - 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022). doi: 10.1109/CASES55004.2022.00023

Work-in-Progress: Efficient Low-latency Near-Memory Addition

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

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