Work-in-progress: Mitigating write disturbance in phase change memory architectures

Chao Hsuan Huang, Ishan G. Thakkar

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Phase Change Memory (PCM) is seen as a potential candidate that can replace DRAM as main memory, due to its better scalability. However, writing '0s' in PCM cells requires high-temperature RESET operations, which induce write disturbance errors in neighboring idle PCM cells due to excessive heat dissipation. This paper introduces low-temperature partial-RESET operations for writing '0s' in PCM cells. Compared to traditional RESET operations, partial-RESET operations dissipate negligible heat, and therefore, do not cause disturbance errors in neighboring cells during PCM writes.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019
ISBN (Electronic)9781450369251
DOIs
StatePublished - Oct 13 2019
Event2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems, CASES 2019 - New York, United States
Duration: Oct 13 2019Oct 18 2019

Publication series

NameProceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019

Conference

Conference2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems, CASES 2019
Country/TerritoryUnited States
CityNew York
Period10/13/1910/18/19

Bibliographical note

Publisher Copyright:
© 2019 Association for Computing Machinery.

Keywords

  • Phase Change Memory (PCM)
  • Reliability
  • Reset Operation
  • Write Disturbance

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Optimization

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