Work-in-progress: Mitigating write disturbance in phase change memory architectures

Chao Hsuan Huang; Ishan G. Thakkar

doi:10.1145/3349569.3351539

Work-in-progress: Mitigating write disturbance in phase change memory architectures

Chao Hsuan Huang, Ishan G. Thakkar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Phase Change Memory (PCM) is seen as a potential candidate that can replace DRAM as main memory, due to its better scalability. However, writing '0s' in PCM cells requires high-temperature RESET operations, which induce write disturbance errors in neighboring idle PCM cells due to excessive heat dissipation. This paper introduces low-temperature partial-RESET operations for writing '0s' in PCM cells. Compared to traditional RESET operations, partial-RESET operations dissipate negligible heat, and therefore, do not cause disturbance errors in neighboring cells during PCM writes.

Original language	English
Title of host publication	Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019
ISBN (Electronic)	9781450369251
DOIs	https://doi.org/10.1145/3349569.3351539
State	Published - Oct 13 2019
Event	2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems, CASES 2019 - New York, United States Duration: Oct 13 2019 → Oct 18 2019

Publication series

Name	Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019

Conference

Conference	2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems, CASES 2019
Country/Territory	United States
City	New York
Period	10/13/19 → 10/18/19

Bibliographical note

Publisher Copyright:
© 2019 Association for Computing Machinery.

Keywords

Phase Change Memory (PCM)
Reliability
Reset Operation
Write Disturbance

ASJC Scopus subject areas

Hardware and Architecture
Control and Optimization

Access to Document

10.1145/3349569.3351539

Cite this

Huang, C. H., & Thakkar, I. G. (2019). Work-in-progress: Mitigating write disturbance in phase change memory architectures. In Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019 Article a7 (Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019). https://doi.org/10.1145/3349569.3351539

Huang, Chao Hsuan ; Thakkar, Ishan G. / Work-in-progress : Mitigating write disturbance in phase change memory architectures. Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019. 2019. (Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019).

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abstract = "Phase Change Memory (PCM) is seen as a potential candidate that can replace DRAM as main memory, due to its better scalability. However, writing '0s' in PCM cells requires high-temperature RESET operations, which induce write disturbance errors in neighboring idle PCM cells due to excessive heat dissipation. This paper introduces low-temperature partial-RESET operations for writing '0s' in PCM cells. Compared to traditional RESET operations, partial-RESET operations dissipate negligible heat, and therefore, do not cause disturbance errors in neighboring cells during PCM writes.",

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Huang, CH & Thakkar, IG 2019, Work-in-progress: Mitigating write disturbance in phase change memory architectures. in Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019., a7, Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019, 2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems, CASES 2019, New York, United States, 10/13/19. https://doi.org/10.1145/3349569.3351539

Work-in-progress: Mitigating write disturbance in phase change memory architectures. / Huang, Chao Hsuan; Thakkar, Ishan G.
Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019. 2019. a7 (Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Phase Change Memory (PCM) is seen as a potential candidate that can replace DRAM as main memory, due to its better scalability. However, writing '0s' in PCM cells requires high-temperature RESET operations, which induce write disturbance errors in neighboring idle PCM cells due to excessive heat dissipation. This paper introduces low-temperature partial-RESET operations for writing '0s' in PCM cells. Compared to traditional RESET operations, partial-RESET operations dissipate negligible heat, and therefore, do not cause disturbance errors in neighboring cells during PCM writes.

AB - Phase Change Memory (PCM) is seen as a potential candidate that can replace DRAM as main memory, due to its better scalability. However, writing '0s' in PCM cells requires high-temperature RESET operations, which induce write disturbance errors in neighboring idle PCM cells due to excessive heat dissipation. This paper introduces low-temperature partial-RESET operations for writing '0s' in PCM cells. Compared to traditional RESET operations, partial-RESET operations dissipate negligible heat, and therefore, do not cause disturbance errors in neighboring cells during PCM writes.

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Huang CH, Thakkar IG. Work-in-progress: Mitigating write disturbance in phase change memory architectures. In Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019. 2019. a7. (Proceedings of the International Conference on Compliers, Architectures and Synthesis for Embedded Systems Companion, CASES 2019). doi: 10.1145/3349569.3351539

Work-in-progress: Mitigating write disturbance in phase change memory architectures

Abstract

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Bibliographical note

Keywords

ASJC Scopus subject areas

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