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A need of quantum computing: "Reversible logic synthesis of parallel binary adder-subtractor"

  • Himanshu Thapliyal
  • , M. B. Srinivas
  • , Hamid R. Arabnia

Producción científica: Conference contributionrevisión exhaustiva

9 Citas (Scopus)

Resumen

Earlier research has proved that a finite amount of energy dissipation would occur if the computation is devoid of reversible logic. In the light of this problem, a binary parallel adder-subtractor using reversible logic is proposed. The proposed circuit has the ability to add and subtract two 4-bit binary numbers depending on the mode bit M. This circuit can be generalized for N bit addition and subtraction. The proposed design technique uses minimum number of gates as well as garbage outputs thereby significantly reducing the circuit complexity.

Idioma originalEnglish
Título de la publicación alojadaProceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05
Páginas60-66
Número de páginas7
EstadoPublished - 2005
Evento2005 International Conference on Embedded Systems and Applications, ESA'05 - Las Vegas, NV, United States
Duración: jun 27 2005jun 30 2005

Serie de la publicación

NombreProceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05

Conference

Conference2005 International Conference on Embedded Systems and Applications, ESA'05
País/TerritorioUnited States
CiudadLas Vegas, NV
Período6/27/056/30/05

ASJC Scopus subject areas

  • Artificial Intelligence
  • Hardware and Architecture
  • Control and Systems Engineering

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