Resumen
Bit-serial SIMD-parallel execution was once commonly used in supercomputers, but fell out of favor as it became practical to implement word-level operations directly in MIMD hardware. Word-level primitive operations simplify programming and significantly speed-up sequential code. However, aggressive gate-level compiler optimization can dramatically reduce power consumed in massively-parallel bit-serial execution without a performance penalty. The model described here, Parallel Bit Pattern Computing, not only leverages gate-level just-in-time optimization of bit-serial code, but also uses a quantum-inspired type of symbolic execution based on regular expressions to obtain a potentially exponential reduction in computational complexity while using entirely conventional computer hardware.
| Idioma original | English |
|---|---|
| Título de la publicación alojada | Languages and Compilers for Parallel Computing - 33rd International Workshop, LCPC 2020 |
| Editores | Barbara Chapman, José Moreira |
| Páginas | 151-159 |
| Número de páginas | 9 |
| DOI | |
| Estado | Published - 2022 |
| Evento | 33rd International Workshop on Languages and Compilers for Parallel Computing, LCPC 2020 - Virtual, Online Duración: oct 14 2020 → oct 16 2020 |
Serie de la publicación
| Nombre | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Volumen | 13149 LNCS |
| ISSN (versión impresa) | 0302-9743 |
| ISSN (versión digital) | 1611-3349 |
Conference
| Conference | 33rd International Workshop on Languages and Compilers for Parallel Computing, LCPC 2020 |
|---|---|
| Ciudad | Virtual, Online |
| Período | 10/14/20 → 10/16/20 |
Nota bibliográfica
Publisher Copyright:© 2022, Springer Nature Switzerland AG.
ASJC Scopus subject areas
- Theoretical Computer Science
- General Computer Science
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