@inproceedings{699e7cd3f47d42a6b671a3c3e68ab76d,
title = "A time-area- power efficient multiplier and square architecture based on ancient Indian Vedic Mathematics",
abstract = "In this paper new multiplier and square architecture is proposed based on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications. It is based on generating all partial products and their sums in one step. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -6. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication and square algorithm implemented in coprocessors. In FPGA implementation it has been found that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier.",
keywords = "Array Multiplier, Multiplier, Square Architecture, Vedic Mathematics",
author = "Himanshu Thapliyal and Arabnia, \{Hamid R.\}",
year = "2004",
language = "English",
isbn = "1932415416",
series = "Proceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04",
pages = "434--439",
editor = "H.R. Arabnia and M. Guo and L.T. Yang",
booktitle = "Proceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the INternational Conference on VLSI, VLSI'04",
note = "Proceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04 ; Conference date: 21-06-2004 Through 24-06-2004",
}