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Design and analysis of A VLSI based high performance low power parallel square architecture

  • Himanshu Thapliyal
  • , M. B. Srinivas
  • , Hamid R. Arabnia

Producción científica: Conference contributionrevisión exhaustiva

16 Citas (Scopus)

Resumen

The present paper proposes a novel square algorithm and architecture based on the Duplex property of Urdhva Triyakbhyam (the multiplication algorithm given in the ancient Indian Vedic Mathematics). It is an object of the present paper to provide a square computation circuit which can reduce circuit size by eliminating unnecessary logic in comparison to computing the square with a dedicated multiplier. The proposed architecture is efficient in terms of silicon area/speed/power compared to using multipliers for performing square operation.

Idioma originalEnglish
Título de la publicación alojadaProceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, AMCS'05
Páginas72-76
Número de páginas5
EstadoPublished - 2005
Evento2005 International Conference on Algorithmic Mathematics and Computer Science, AMCS'05 - Las Vegas, NV, United States
Duración: jun 20 2005jun 23 2005

Serie de la publicación

NombreProceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, AMCS'05

Conference

Conference2005 International Conference on Algorithmic Mathematics and Computer Science, AMCS'05
País/TerritorioUnited States
CiudadLas Vegas, NV
Período6/20/056/23/05

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications
  • Theoretical Computer Science

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