Design for a fast and low power 2's complement multiplier

This paper proposes high speed two's complement parallel multiplier architecture for low power and high speed applications. The proposed two's complement NXN bit multiplier architecture is based on two concepts: the partial products can be generated in parallel with a delay of d and thereafter the addition can be reduced to log2N steps. The most significant aspect of the proposed architecture is that any future proposed efficient adder can be implemented in the proposed multiplier, without changing the original hardware architecture thereby improving its efficiency to a great extent. The coding is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. As the number of bits in multiplier increases,the result shows that the proposed multiplier architecture can be of great significance in terms of area and speed.