Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

C. Labrado; H. Thapliyal

doi:10.1049/el.2016.2294

Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

C. Labrado
, H. Thapliyal

Electrical and Computer Engineering

Producción científica: Article › revisión exhaustiva

3 Citas (Scopus)

Resumen

Implementation of a five-input majority gate, full adder, and full subtractor using multiple layers in nanomagnetic logic is proposed. Correct functionality of the designs was verified through the use of a special purpose Verilog library.

Idioma original	English
Páginas (desde-hasta)	1618-1620
Número de páginas	3
Publicación	Electronics Letters
Volumen	52
N.º	19
DOI	https://doi.org/10.1049/el.2016.2294
Estado	Published - sept 15 2016

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Publisher Copyright:
© The Institution of Engineering and Technology 2016.

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el.2016.2294

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Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

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