Energy-Efficient Design of Hybrid MTJ/CMOS and MTJ/Nanoelectronics Circuits

As CMOS technology scales down to the nanoscale, high leakage power consumption becomes one of the major concerns in the design of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory (LIM) structures are being studied. Magnetic tunnel junction (MTJ) is an emerging spin-based device, which consumes very minimal leakage power in conjunction with CMOS transistors. In this paper, we propose a novel MTJ/CMOS design, which consumes low power and has lower delay than the existing LIM-based MTJ/CMOS designs. The proposed MTJ/CMOS designs have lower power and lower delay by charge sharing the output nodes during the pre-charge phase. The designs are simulated using 45 nm CMOS technology with perpendicular anistropy CoFeB/MgO MTJ model using a Cadence Spectre simulator. From the simulation results, we can see that the proposed MTJ/CMOS OR, AND, XOR, MUX, and full adder designs have 31.35%, 40.15%, 49.17%, 35.86%, and 42.62% lower power-delay-product, respectively, compared with the existing MTJ/CMOS designs. Furthermore, in this paper, we have also studied the usage of integrating nano-electronic devices, such as a carbon nanotube field-effect transistor and a Fin field-effect transistor, in the proposed circuits along with the MTJ devices.