Faster RSA encryption/decryption architecture using an efficient high speed overlay multiplier

Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia

Faster RSA encryption/decryption architecture using an efficient high speed overlay multiplier

Himanshu Thapliyal
, M. B. Srinivas
, Hamid R. Arabnia

Electrical and Computer Engineering

Producción científica: Conference contribution › revisión exhaustiva

Resumen

This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed hierarchical overlay multiplier architecture. In the hierarchical overlay architecture, we have grouped 4 bits of the multiplier and multiplicand at a time and thereafter apply vertical and crosswise algorithm to decompose whole of the multiplication operation into 4×4 parallel multiply modules. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithms.

Idioma original	English
Título de la publicación alojada	Proceedings of The 2005 International Conference on Security and Management, SAM'05
Páginas	40-44
Número de páginas	5
Estado	Published - 2005
Evento	2005 International Conference on Security and Management, SAM'05 - Las Vegas, NV, United States Duración: jun 20 2005 → jun 23 2005

Serie de la publicación

Nombre	Proceedings of The 2005 International Conference on Security and Management, SAM'05

Conference

Conference	2005 International Conference on Security and Management, SAM'05
País/Territorio	United States
Ciudad	Las Vegas, NV
Período	6/20/05 → 6/23/05

Nota bibliográfica

Funding Information:
The authors wish to thank L. Liu at the College of Geoscience of Northeast Petroleum University for her constructive help. The authors are particularly grateful to S. Busetti, L. Zeng, Z. Liao, and the anonymous reviewers for providing excellent advice on the clarity of the text and figures. This study is financially supported by the National Natural Science Foundation of China (grant nos. 41502124 and U1562214) and China Postdoctoral Science Foundation (grant no. 2015M581424).

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Software

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@inproceedings{f4605509fe4e442eb83c41bbf89f86b1,

title = "Faster RSA encryption/decryption architecture using an efficient high speed overlay multiplier",

abstract = "This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed hierarchical overlay multiplier architecture. In the hierarchical overlay architecture, we have grouped 4 bits of the multiplier and multiplicand at a time and thereafter apply vertical and crosswise algorithm to decompose whole of the multiplication operation into 4×4 parallel multiply modules. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithms.",

author = "Himanshu Thapliyal and Srinivas, \{M. B.\} and Arabnia, \{Hamid R.\}",

note = "Funding Information: The authors wish to thank L. Liu at the College of Geoscience of Northeast Petroleum University for her constructive help. The authors are particularly grateful to S. Busetti, L. Zeng, Z. Liao, and the anonymous reviewers for providing excellent advice on the clarity of the text and figures. This study is financially supported by the National Natural Science Foundation of China (grant nos. 41502124 and U1562214) and China Postdoctoral Science Foundation (grant no. 2015M581424).; 2005 International Conference on Security and Management, SAM'05 ; Conference date: 20-06-2005 Through 23-06-2005",

year = "2005",

language = "English",

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series = "Proceedings of The 2005 International Conference on Security and Management, SAM'05",

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Thapliyal, H, Srinivas, MB & Arabnia, HR 2005, Faster RSA encryption/decryption architecture using an efficient high speed overlay multiplier. En Proceedings of The 2005 International Conference on Security and Management, SAM'05. Proceedings of The 2005 International Conference on Security and Management, SAM'05, pp. 40-44, 2005 International Conference on Security and Management, SAM'05, Las Vegas, NV, United States, 6/20/05.

Faster RSA encryption/decryption architecture using an efficient high speed overlay multiplier. / Thapliyal, Himanshu; Srinivas, M. B.; Arabnia, Hamid R.
Proceedings of The 2005 International Conference on Security and Management, SAM'05. 2005. p. 40-44 (Proceedings of The 2005 International Conference on Security and Management, SAM'05).

Producción científica: Conference contribution › revisión exhaustiva

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AU - Srinivas, M. B.

AU - Arabnia, Hamid R.

N1 - Funding Information: The authors wish to thank L. Liu at the College of Geoscience of Northeast Petroleum University for her constructive help. The authors are particularly grateful to S. Busetti, L. Zeng, Z. Liao, and the anonymous reviewers for providing excellent advice on the clarity of the text and figures. This study is financially supported by the National Natural Science Foundation of China (grant nos. 41502124 and U1562214) and China Postdoctoral Science Foundation (grant no. 2015M581424).

PY - 2005

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N2 - This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed hierarchical overlay multiplier architecture. In the hierarchical overlay architecture, we have grouped 4 bits of the multiplier and multiplicand at a time and thereafter apply vertical and crosswise algorithm to decompose whole of the multiplication operation into 4×4 parallel multiply modules. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithms.

AB - This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed hierarchical overlay multiplier architecture. In the hierarchical overlay architecture, we have grouped 4 bits of the multiplier and multiplicand at a time and thereafter apply vertical and crosswise algorithm to decompose whole of the multiplication operation into 4×4 parallel multiply modules. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithms.

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BT - Proceedings of The 2005 International Conference on Security and Management, SAM'05

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Faster RSA encryption/decryption architecture using an efficient high speed overlay multiplier

Resumen

Serie de la publicación

Conference

Nota bibliográfica

ASJC Scopus subject areas

Otros archivos y enlaces

Huella

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