High speed efficient N bit by N bit division algorithm and architecture based on ancient Indian vedic mathematics

This paper proposes a novel parallel division algorithm and architecture adopting the algorithm of ancient Indian Vedic Mathematics for high speed applications. In the proposed architecture, the grouping of bits 4 at time is done for operands (dividend and divisor). The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopsys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -4. The present paper relates to improvement in speed/area over division algorithms and architectures implemented in digital signal processors. In FPGA implementation it has been found that the proposed division algorithm and architecture is faster than architectures based on restore and non restore division algorithms.