@inproceedings{a147a7157a654ee0a9c681e03ee74310,
title = "Implementation of a fast square in RSA encryption/decryption architecture",
abstract = "This paper proposes the hardware implementation of RSA encryption algorithm using the recently proposed square architecture. It is an object of the present paper to provide a RSA encryption/ decryption circuit which can reduce circuit size by eliminating unnecessary logic in comparison to computing the square with a dedicated multiplier. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that RSA hardware implemented using the proposed architecture is faster than RSA hardware implemented using traditional multiplication algorithm.",
author = "Himanshu Thapliyal and Srinivas, \{M. B.\} and Arabnia, \{Hamid R.\}",
year = "2005",
language = "English",
isbn = "1932415823",
series = "Proceedings of The 2005 International Conference on Security and Management, SAM'05",
pages = "371--374",
booktitle = "Proceedings of The 2005 International Conference on Security and Management, SAM'05",
note = "2005 International Conference on Security and Management, SAM'05 ; Conference date: 20-06-2005 Through 23-06-2005",
}