Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems

I. C. Kizilyalli; G. C. Abeln; Z. Chen; J. Lee; G. Weber; B. Kotzias; S. Chetlur; J. W. Lyding; K. Hess

doi:10.1109/55.728907

Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems

I. C. Kizilyalli
, G. C. Abeln
, Z. Chen
, J. Lee
, G. Weber
, B. Kotzias
, S. Chetlur
, J. W. Lyding
, K. Hess

Producción científica: Article › revisión exhaustiva

25 Citas (Scopus)

Resumen

This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient Is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal art still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes.

Idioma original	English
Páginas (desde-hasta)	444-446
Número de páginas	3
Publicación	IEEE Electron Device Letters
Volumen	19
N.º	11
DOI	https://doi.org/10.1109/55.728907
Estado	Published - nov 1998

Nota bibliográfica

Funding Information:
Manuscript received April 1, 1998; revised July 30, 1998. The work of K. Hess was supported by the Office of Naval Research and the Army Research Office. The work of J. Lee was supported by the Office of Naval Research and the Beckmann Institute for Advanced Science and Technology. I. C. Kizilyalli, B. Kotzias, and S. Chetlur are with the Lucent Technologies, Bell Laboratories, Orlando, FL 32819 USA (e-mail: [email protected]). G. C. Abeln, Z. Chen, J. Lee, J. W. Lyding, and K. Hess are with the Beckman Institute, University of Illinois, Urbana, IL 61801 USA. G. Weber is with the Lucent Technologies, Bell Laboratories, Murray Hill, NJ 07974 USA. Publisher Item Identifier S 0741-3106(98)08496-1.

Financiación

Manuscript received April 1, 1998; revised July 30, 1998. The work of K. Hess was supported by the Office of Naval Research and the Army Research Office. The work of J. Lee was supported by the Office of Naval Research and the Beckmann Institute for Advanced Science and Technology. I. C. Kizilyalli, B. Kotzias, and S. Chetlur are with the Lucent Technologies, Bell Laboratories, Orlando, FL 32819 USA (e-mail: [email protected]). G. C. Abeln, Z. Chen, J. Lee, J. W. Lyding, and K. Hess are with the Beckman Institute, University of Illinois, Urbana, IL 61801 USA. G. Weber is with the Lucent Technologies, Bell Laboratories, Murray Hill, NJ 07974 USA. Publisher Item Identifier S 0741-3106(98)08496-1.

Financiadores
Beckmann Institute for Advanced Science and Technology
Office of Naval Research
Army Research Office

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Acceder al documento

10.1109/55.728907

Otros archivos y enlaces

Citar esto

@article{9ac4ebd40bd74d6e8d6ca0928ab22931,

title = "Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems",

abstract = "This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient Is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal art still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes.",

author = "Kizilyalli, \{I. C.\} and Abeln, \{G. C.\} and Z. Chen and J. Lee and G. Weber and B. Kotzias and S. Chetlur and Lyding, \{J. W.\} and K. Hess",

note = "Funding Information: Manuscript received April 1, 1998; revised July 30, 1998. The work of K. Hess was supported by the Office of Naval Research and the Army Research Office. The work of J. Lee was supported by the Office of Naval Research and the Beckmann Institute for Advanced Science and Technology. I. C. Kizilyalli, B. Kotzias, and S. Chetlur are with the Lucent Technologies, Bell Laboratories, Orlando, FL 32819 USA (e-mail: [email protected]). G. C. Abeln, Z. Chen, J. Lee, J. W. Lyding, and K. Hess are with the Beckman Institute, University of Illinois, Urbana, IL 61801 USA. G. Weber is with the Lucent Technologies, Bell Laboratories, Murray Hill, NJ 07974 USA. Publisher Item Identifier S 0741-3106(98)08496-1.",

year = "1998",

month = nov,

doi = "10.1109/55.728907",

language = "English",

volume = "19",

pages = "444--446",

number = "11",

}

TY - JOUR

T1 - Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems

AU - Kizilyalli, I. C.

AU - Abeln, G. C.

AU - Chen, Z.

AU - Lee, J.

AU - Weber, G.

AU - Kotzias, B.

AU - Chetlur, S.

AU - Lyding, J. W.

AU - Hess, K.

N1 - Funding Information: Manuscript received April 1, 1998; revised July 30, 1998. The work of K. Hess was supported by the Office of Naval Research and the Army Research Office. The work of J. Lee was supported by the Office of Naval Research and the Beckmann Institute for Advanced Science and Technology. I. C. Kizilyalli, B. Kotzias, and S. Chetlur are with the Lucent Technologies, Bell Laboratories, Orlando, FL 32819 USA (e-mail: [email protected]). G. C. Abeln, Z. Chen, J. Lee, J. W. Lyding, and K. Hess are with the Beckman Institute, University of Illinois, Urbana, IL 61801 USA. G. Weber is with the Lucent Technologies, Bell Laboratories, Murray Hill, NJ 07974 USA. Publisher Item Identifier S 0741-3106(98)08496-1.

PY - 1998/11

Y1 - 1998/11

N2 - This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient Is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal art still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes.

AB - This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient Is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal art still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes.

UR - https://www.scopus.com/pages/publications/0032206525

UR - https://www.scopus.com/pages/publications/0032206525#tab=citedBy

U2 - 10.1109/55.728907

DO - 10.1109/55.728907

M3 - Article

AN - SCOPUS:0032206525

SN - 0741-3106

VL - 19

SP - 444

EP - 446

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 11

ER -

Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems

Resumen

Nota bibliográfica

Financiación

ASJC Scopus subject areas

Acceder al documento

Otros archivos y enlaces

Huella

Citar esto