Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function

Yasuhiro Takahashi; Hiroki Koyasu; S. Dinesh Kumar; Himanshu Thapliyal

doi:10.1109/ISVLSI.2019.00086

Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function

Yasuhiro Takahashi
, Hiroki Koyasu
, S. Dinesh Kumar
, Himanshu Thapliyal

Electrical and Computer Engineering

Producción científica: Conference contribution › revisión exhaustiva

5 Citas (Scopus)

Resumen

Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.

Idioma original	English
Título de la publicación alojada	Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
Páginas	443-446
Número de páginas	4
ISBN (versión digital)	9781538670996
DOI	https://doi.org/10.1109/ISVLSI.2019.00086
Estado	Published - jul 2019
Evento	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 - Miami, United States Duración: jul 15 2019 → jul 17 2019

Serie de la publicación

Nombre	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volumen	2019-July
ISSN (versión impresa)	2159-3469
ISSN (versión digital)	2159-3477

Conference

Conference	18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
País/Territorio	United States
Ciudad	Miami
Período	7/15/19 → 7/17/19

Nota bibliográfica

Publisher Copyright:
© 2019 IEEE.

Financiación

This work was supported by VLSI Design and Educational Center (VDEC), the University of Tokyo in collaboration with Cadence Corporation and Synopsys, Inc. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with ROHM Corporation and Toppan Printing Corporation.

Financiadores
University of Tokyo

ODS de las Naciones Unidas

Este resultado contribuye a los siguientes Objetivos de Desarrollo Sostenible

Affordable and clean energy

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/ISVLSI.2019.00086

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Takahashi, Y., Koyasu, H., Kumar, S. D., & Thapliyal, H. (2019). Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. En Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 (pp. 443-446). Artículo 8839442 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July). https://doi.org/10.1109/ISVLSI.2019.00086

@inproceedings{0ba9930ad2594949a6829fddbb418ef1,

title = "Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function",

abstract = "Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.",

keywords = "Adiabatic logic, PUF, hardware security, low-power",

author = "Yasuhiro Takahashi and Hiroki Koyasu and Kumar, \{S. Dinesh\} and Himanshu Thapliyal",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019 ; Conference date: 15-07-2019 Through 17-07-2019",

year = "2019",

month = jul,

doi = "10.1109/ISVLSI.2019.00086",

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Takahashi, Y, Koyasu, H, Kumar, SD & Thapliyal, H 2019, Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. En Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019., 8839442, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2019-July, pp. 443-446, 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, United States, 7/15/19. https://doi.org/10.1109/ISVLSI.2019.00086

Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. / Takahashi, Yasuhiro; Koyasu, Hiroki; Kumar, S. Dinesh et al.
Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019. 2019. p. 443-446 8839442 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2019-July).

Producción científica: Conference contribution › revisión exhaustiva

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T1 - Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function

AU - Takahashi, Yasuhiro

AU - Koyasu, Hiroki

AU - Kumar, S. Dinesh

AU - Thapliyal, Himanshu

PY - 2019/7

Y1 - 2019/7

N2 - Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.

AB - Silicon based Physical Unclonable Function (PUF) is a popular hardware security primitive for mitigating security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) was first proposed by Kumar and Thapliyal. QUALPUF has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such RFIDs, wireless sensor nodes, etc. In this paper, we present the post-layout simulation results of the 4-bit QUALPUF for low-power portable electronic devices. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 um standard CMOS process with 1.8 V supply voltage. The QUALPUF occupies 58.7x15.7 um2 of layout area. The post-layout simulation results illustrate that the 4-bit QUALPUF has good uniqueness and reliability with 29.73 fJ/cycle/bit energy consumption.

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KW - PUF

KW - hardware security

KW - low-power

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Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function

Resumen

Serie de la publicación

Conference

Nota bibliográfica

Financiación

ODS de las Naciones Unidas

ASJC Scopus subject areas

Acceder al documento

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