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Quantum circuit designs of integer division optimizing T-count and T-depth

  • Himanshu Thapliyal
  • , T. S.S. Varun
  • , Edgard Munoz-Coreas
  • , Keith A. Britt
  • , Travis S. Humble

Producción científica: Conference contributionrevisión exhaustiva

17 Citas (Scopus)

Resumen

Quantum circuits for basic mathematical functions such as division are required to implement scientific computing algorithms on quantum computers. In this work, we propose two designs for quantum integer division. The designs are based on quantum Clifford+T gates and are optimized for T-count and T-depth. Quantum circuits that are based on Clifford+T gates can be made fault tolerant in nature but the T gate is very costly to implement. As a result, reducing T-count and T-depth have become important optimization goals. Existing quantum hardware is limited in terms of number of available qubits. Thus, ancillary qubits are a circuit overhead that needs to be kept to a minimum. We propose two quantum integer division circuits. The first quantum integer division circuit is based on the non-restoring division algorithm. The proposed non-restoring division circuit is optimized for total quantum hardware (T-count and T-depth) cost but requires 2∗ n + 1 ancillary qubits. We also propose a quantum integer division circuit based on the restoring division algorithm. The proposed restoring division circuit is optimized for total qubits. The design requires only n ancillary qubits but will need more quantum hardware than the non-restoring division circuit. Both proposed quantum circuits are based on (i) a new quantum conditional addition circuit, (ii) a new quantum adder-subtractor and (iii) a new quantum subtraction circuit. Further, both designs are compared and shown to be superior to existing work in terms of T-count and T-depth. The proposed quantum non-restoring integer division circuit has a 96% improvement in terms of T-count and a 93% improvement in terms of T-depth compared to existing work. The proposed quantum restoring integer division circuit has a 91% improvement in terms of T-count and a 86% improvement in terms of T-count compared to the existing work.

Idioma originalEnglish
Título de la publicación alojadaProceedings - 2017 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017
Páginas123-128
Número de páginas6
ISBN (versión digital)9781538613566
DOI
EstadoPublished - jul 2 2017
Evento3rd IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017 - Bhopal, India
Duración: dic 18 2017dic 20 2017

Serie de la publicación

NombreProceedings - 2017 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017
Volumen2018-February

Conference

Conference3rd IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017
País/TerritorioIndia
CiudadBhopal
Período12/18/1712/20/17

Nota bibliográfica

Publisher Copyright:
© 2017 IEEE.

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Computer Science Applications

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