Reduction of cache coherence overhead by compiler data layout and loop transformation

Y. J. Ju; H. Dietz

doi:10.1007/bfb0038675

Reduction of cache coherence overhead by compiler data layout and loop transformation

Y. J. Ju, H. Dietz

Producción científica: Conference contribution › revisión exhaustiva

25 Citas (Scopus)

Resumen

This paper presents a systematic approach that integrates compiler optimization of data layout and traditional loop transformations to reduce cache coherence overhead. A formal model based on an interference graph, overview of the optimization algorithms, and an example are given. Excerpts from an empirical evaluation of the complexity of the compiler analysis, and the simulation study of the resulting reductions in bus traffic and execution time, are also presented. Additional details appear in [7].

Idioma original	English
Título de la publicación alojada	Languages and Compilers for Parallel Computing - 4th International Workshop, Proceedings
Editores	Utpal Banerjee, David Gelernter, Alex Nicolau, David Padua
Páginas	344-358
Número de páginas	15
DOI	https://doi.org/10.1007/bfb0038675
Estado	Published - 1992
Evento	4th Workshop on Languages and Compilers for Parallel Computing, 1991 - Santa Clara, United States Duración: ago 7 1991 → ago 9 1991

Serie de la publicación

Nombre	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volumen	589 LNCS
ISSN (versión impresa)	0302-9743
ISSN (versión digital)	1611-3349

Conference

Conference	4th Workshop on Languages and Compilers for Parallel Computing, 1991
País/Territorio	United States
Ciudad	Santa Clara
Período	8/7/91 → 8/9/91

Nota bibliográfica

Publisher Copyright:
© 1992, Springer Verlag. All rights reserved.

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

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10.1007/bfb0038675

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Ju, Y. J., & Dietz, H. (1992). Reduction of cache coherence overhead by compiler data layout and loop transformation. En U. Banerjee, D. Gelernter, A. Nicolau, & D. Padua (Eds.), Languages and Compilers for Parallel Computing - 4th International Workshop, Proceedings (pp. 344-358). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 589 LNCS). https://doi.org/10.1007/bfb0038675

Ju, Y. J. ; Dietz, H. / Reduction of cache coherence overhead by compiler data layout and loop transformation. Languages and Compilers for Parallel Computing - 4th International Workshop, Proceedings. editor / Utpal Banerjee ; David Gelernter ; Alex Nicolau ; David Padua. 1992. pp. 344-358 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "This paper presents a systematic approach that integrates compiler optimization of data layout and traditional loop transformations to reduce cache coherence overhead. A formal model based on an interference graph, overview of the optimization algorithms, and an example are given. Excerpts from an empirical evaluation of the complexity of the compiler analysis, and the simulation study of the resulting reductions in bus traffic and execution time, are also presented. Additional details appear in [7].",

author = "Ju, \{Y. J.\} and H. Dietz",

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Ju, YJ & Dietz, H 1992, Reduction of cache coherence overhead by compiler data layout and loop transformation. En U Banerjee, D Gelernter, A Nicolau & D Padua (eds.), Languages and Compilers for Parallel Computing - 4th International Workshop, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 589 LNCS, pp. 344-358, 4th Workshop on Languages and Compilers for Parallel Computing, 1991, Santa Clara, United States, 8/7/91. https://doi.org/10.1007/bfb0038675

Reduction of cache coherence overhead by compiler data layout and loop transformation. / Ju, Y. J.; Dietz, H.
Languages and Compilers for Parallel Computing - 4th International Workshop, Proceedings. ed. / Utpal Banerjee; David Gelernter; Alex Nicolau; David Padua. 1992. p. 344-358 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 589 LNCS).

Producción científica: Conference contribution › revisión exhaustiva

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Ju YJ, Dietz H. Reduction of cache coherence overhead by compiler data layout and loop transformation. En Banerjee U, Gelernter D, Nicolau A, Padua D, editores, Languages and Compilers for Parallel Computing - 4th International Workshop, Proceedings. 1992. p. 344-358. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/bfb0038675

Reduction of cache coherence overhead by compiler data layout and loop transformation

Resumen

Serie de la publicación

Conference

Nota bibliográfica

ASJC Scopus subject areas

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