TY - GEN
T1 - The new BCD subtractor and its reversible logic implementation
AU - Thapliyal, Himanshu
AU - Srinivas, M. B.
PY - 2006
Y1 - 2006
N2 - IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Thus in this paper we propose a novel BCD subtracter called carry skip BCD subtracter. We also propose the reversible logic implementation of the proposed carry skip BCD subtracter. Reversible logic is emerging as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. It is being tried to design the BCD subtracter optimal in terms of number of reversible gates and garbage outputs.
AB - IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Thus in this paper we propose a novel BCD subtracter called carry skip BCD subtracter. We also propose the reversible logic implementation of the proposed carry skip BCD subtracter. Reversible logic is emerging as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. It is being tried to design the BCD subtracter optimal in terms of number of reversible gates and garbage outputs.
UR - https://www.scopus.com/pages/publications/33845191709
UR - https://www.scopus.com/pages/publications/33845191709#tab=citedBy
U2 - 10.1007/11859802_45
DO - 10.1007/11859802_45
M3 - Conference contribution
AN - SCOPUS:33845191709
SN - 3540400567
SN - 9783540400561
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 466
EP - 472
BT - Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
T2 - 11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006
Y2 - 6 September 2006 through 8 September 2006
ER -